About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of... tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Marvell's Optical PHY team develops advanced ultra high speed broadband transceivers. These advanced transceivers consist of broadband equalization circuitries (CTLE, FFE and DFE), ultra high speed data converters (ADCs and DACs) and high performance (very high frequency and very low jitter) clock generation and clock distribution.Our innovative approaches have resulted in the company’s products being first to market in many of key areas, including opto-electronics and DSP based transceivers providing most advanced chips and subsystems solutions to address todays and future multi-100Gig interconnect requirements for the ever-increasing demand of higher data rates. We are seeking talented individuals to work on solving technical challenges with the most outstanding group of collaborators in the industry. Join our team of experts and make a difference in an exciting career opportunity.
What You Can Expect
As an Analog/Mixed-Signal IC Design Engineer, you will be part of a key team designing highly sophisticated CMOS transceiver/SERDES products.  Responsibilities would include implementation and verification of circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, CDRs etc. to meet key performance targets and performing design verification using industry standard tools such as Spectre, MATLAB etc.

What We're Looking For
- Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5+ years of experience.


To succeed in this role, you must have the following:
- Hands-on experience in designing mixed signal circuits including ADCs, DACs, RX, TX, PLLs, Filters, Bandgap bias circuits, regulators, and other analog circuits.

- Specialized depth and/or breadth of expertise.

- Ability to apply innovative solutions to resolve complex issues.

- History of identifying and developing best practices that deliver high-quality and effective solutions.

- Strong knowledge on the deep sub-micron CMOS technologies.

- Knowledge and experience on low power and high speed design techniques.

- Excellent problem solving and analytical skills.

- Strong knowledge on IC design CAD tools such as Spectre, Spice, Matlab, Hsim, Verilog, etc.

- Lab testing skills to evaluate the prototype unit to the design specification.



Expected Base Pay Range (USD)
167,500 - 247,860, $ per annum
The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements 
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity 
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of... tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

As a Hardware Design Senior Staff Engineer with Marvell, you’ll be a member of the Central Engineering business group. Central Engineering is the center hub providing IP to be used by all BUs across Marvell. In this role, you’ll be part of the the internal Marvell team that manages 3rd party IP management and will work to source IP from external IP suppliers. In this internal role, you will work in parallel with a team of 3rd party IP engineers responsible for bringing in all subcontracted IP under the Marvell IP umbrella. This is a dynamic and challenging role, and you will engage all parts of Marvell including the SoC architecture teams, Business development, Legal, Finance, Sales, and support critical Hyperscalar programs that heavily leverage DDR/LPDDR/HBM Interface IP, that is predominantly 3rd party IP.
What You Can Expect
Looking for a talented Principal Technical IP Engineer to join the Marvell Team to manage 3rd party IP integration engineers to assist Marvell in offering DDR/LPDDR/GDDR/HBM/eMMC memory interface cores to our clients.

Become part of a team creating leading-edge designs for the latest applications in artificial intelligence, automotive, hyper-scaler, communications, and storage. As member of the Marvell team to manage 3rd party core integrator, you will be involved in all stages of SoC development including defining core requirements, validating IP developer competence, overseeing core development, technology compliance, core integration, test compliance and silicon validation. 

You will assist sales in winning bids by working with leading edge IP providers to meet customer requirements.  You will manage 3rd party developers in completing core designs and providing required design rules.  You will advise the Marvell design center on core integration into custom silicon designs and hold joint reviews with the design center and 3rd party IP provider.  Post-silicon validation at customer sites will require a limited degree of travel.  

Responsibilities will also include developing statements of work, leading provider progress reviews, using 3rd party developer problem reporting tools to drive to problem resolution. You will assist with 8D follow-through for significant supplier issues.

What We're Looking For
- BS degree in technical discipline with minimum 7 years of relevant experience. 
- Proficient in understanding of DDR type interfaces (DDR, LPDDR, GDDR, HBM, eMMC), including the challenges associated with SoC PHY integration, timing analysis, packaging, and multi-chip integrated packaging. 
- Proficient in project management tasks required to manage 3rd party developers.  
- Broad-based exposure to ASIC design flows required for releasing a chip to fabrication including logic synthesis, physical design, timing, DRC/LVS, Formal verification and electrical checking 
- Good understanding of Design-For-Test concepts including DFT logic insertion, test generation, scan and embedded core testing 
- Good communication and customer management skills 


Expected Base Pay Range (USD)
143,200 - 214,500, $ per annum
The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements 
At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity 
As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews. Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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